In these years, a large number of liquid crystal display devices with diagonal screen sizes of 5 cm to 100 cm, which can display television images and various images, have already been provided for commercial purposes, owing to the development in techniques such as a microfabrication technique, a liquid crystal material technique, and a high-density mounting technique. Such a liquid crystal display device can easily achieve a color display with a configuration in which colored layers of R, G, and B are provided on one of two glass substrates which constitute a liquid crystal panel. According to a so-called active matrix liquid crystal panel, switching elements are provided for respective pixels, and therefore the active matrix liquid crystal panel could (i) reduce a crosstalk, (ii) achieve a quick response, and (iii) secure an image with high contrast ratio, from the beginning of its commercialization.
According to the liquid crystal display device (liquid crystal panel), in general, approximately 200 to 1200 scanning signal lines (gate lines) and approximately 300 to 1600 data signal lines (source lines) are provided in a matrix manner. In these years, an increase in a screen size and an increase in definition of the liquid crystal display device are being sought concurrently, in order to address an increase in display capacity.
FIG. 13 is a perspective view illustrating a mounting method of a liquid crystal panel disclosed in Patent Literature 1. An electric signal is supplied to an image display section with a mounding method such as (i) a COG (chip-on-glass) method in which a semiconductor integrated circuit chip 3 is connected with an electrode terminal 5 of a scanning signal line with the use of a conductive adhesive, and a driving signal is supplied from the semiconductor integrated circuit chip 3 to the electrode terminal 5 of the scanning signal line, which is provided on one of transparent insulating substrates (e.g., a glass substrate 2) constituting a liquid crystal panel 1, or (ii) a TCP (tape-carrier-package) method in which a TCP film 4, which is made up of a polyimide resin thin film as a base and has a terminal made up of a gold- or solder-plated copper foil, is compression-bonded on an electrode terminal 6 of a data signal line with the use of an appropriate adhesive agent containing a conductive medium. In FIG. 13, two mounting methods are illustrated together for convenience. However, in practice, any one of the methods is to be selected as appropriate.
Pixels in an image display section, which is disposed substantially in the center of the liquid crystal panel 1, are connected with the electrode terminals 5 and 6 of the respective scanning signal line and the data signal line via respective lines indicated by reference numerals 7 and 8. The lines 7 and 8 do not necessarily need to be made of a conductive material identical to that for the electrode terminals 5 and 6. A reference numeral 9 indicates a counter glass substrate or a color filter which is the other of the transparent insulating substrates. The counter glass substrate or the color filter has a surface which (i) faces the one of the transparent insulating substrates and (ii) is provided with a transparent conductive counter electrode, which is common to all liquid crystal cells.
FIG. 14 is an equivalent circuit diagram illustrating an active liquid crystal display device in which an insulated gate transistor 10 is provided as a switching element for each of pixels. In FIG. 14, a reference numeral 11 (corresponding to the reference numeral 7 in FIG. 13) indicates a scanning signal line, a reference numeral 12 (corresponding to the reference numeral 8 in FIG. 13) indicates a data signal line, a reference numeral 13 indicates a liquid crystal cell, which is electrically addressed as a capacitor element. Elements, which are drawn with solid lines, are provided on a glass substrate 2 which is one of glass substrates constituting the liquid crystal panel 1. A counter electrode (common electrode) 14, which is common to all the liquid crystal cells 13 and is drawn with dotted lines, is provided on a main surface, which faces the glass substrate 2, of a glass substrate 9 which is the other of the glass substrates constituting the liquid crystal panel 1. In a case where (i) OFF resistance of the insulated gate transistor 10 or resistance of the liquid crystal cell 13 is low or (ii) a gradation property of a display image is considered as important, the circuit is modified in such a way that an auxiliary storage capacitor (auxiliary capacitor) 15 is added in parallel with the liquid crystal cell 13 in order to increase a time constant of the liquid crystal cell 13 as a load. Note that a reference numeral 16 indicates a storage capacitor line or a counter electrode which serves as a bus line common to the storage capacitors 15.
FIG. 15 is a cross-sectional view illustrating an essential part of the image display section of the liquid crystal display device. As shown in FIG. 15, the two glass substrates 2 and 9, which constitute the liquid crystal panel 1, are provided so as to be away from each other at a predetermined distance (approximately several micrometers) via a resinous fiber, beads, or a spacer such as a columnar spacer provided on the color filter 9 (these members are note illustrated). The space (gap) between the glass substrates 2 and 9 is an enclosed space which is filled with liquid crystal 17 and sealed with (i) a sealing material made of organic resin and (ii) a sealer (these materials are not illustrated) which are provided in a periphery of the glass substrate 9.
In a case where a color display is to be carried out, an organic thin film (referred to as a colored layer 18), which has a thickness of approximately 1 μm to 2 μm and contains one of or both of dye and pigment, is attached to an enclosed space side of the glass substrate 9 so as to achieve a color display function. In such a case, the glass substrate 9 is also referred to as a color filter (CF). Further, a polarizing plate(s) 19 is(are) provided on one of or both of an upper surface of the glass substrate 9 and a lower surface of the glass substrate 2, depending on a characteristic of the liquid crystal material 17 so that the liquid crystal panel 1 serves as an electro-optic device. At present, most of commercially available liquid crystal panels use a TN (twisted nematic) liquid crystal material, and therefore, in general, it is necessary to provide two polarizing plates 19. According to a transmissive liquid crystal panel, a backside light source is provided as a light source, and white light is emitted from beneath (not illustrated).
Polyimide resin thin films 20 are provided between the liquid crystal 17 and the respective glass substrates 2 and 9. Each of the polyimide resin thin films 20 is an alignment film which (i) has a thickness of, for example, approximately 0.1 μm and (ii) causes liquid crystal molecules to be aligned toward a predetermined direction. The insulated gate transistor 10 has a drain which is connected with a transparent conductive pixel electrode 22 via a drain electrode (drain line) which (i) is indicated by a reference numeral 21 and (ii) is usually formed concurrently with a formation of the data signal line (source line) 12. A semiconductor layer 23 (whose details will be described later) is provided between the source electrode 12 and drain electrode 21. A Cr thin film layer 24 having a thickness of approximately 0.1 μm is provided between any adjacent two colored layers 18 on the color filter 9. Note that the Cr thin film layer 24 is a light-shielding member which prevents external light from entering the semiconductor layer 23, the scanning signal line 11, and the data signal line 12. This configuration has been established as a so-called black matrix (BM) arrangement.
In order to produce an active matrix substrate 71, in which scanning signal lines, data signal lines, insulated gate transistors serving as switching elements, and pixel electrodes are provided on the glass substrate 2, it is necessary to carry out a photolithography (photo-etching) more than once with the use of photomasks, as with a production of a semiconductor integrated circuit. Although detailed background is not described here, (i) an islanding process of a semiconductor layer has been rationalized and (ii) a contact formation process with respect to a scanning signal line has been eliminated. Consequently, the number of required photomasks, which was approximately 7 to 8 at the beginning, has been reduced to 5 nowadays, owing to a dry etching technique. This drastically contributes to a reduction in processing cost. It is known that manufacturing cost of a liquid crystal display device can be effectively reduced by attaining the following object in development, i.e., a reduction in (i) processing cost in producing an active matrix substrate and (ii) material cost in assembling a panel and mounting a module. It is therefore self-evident that a reduction in production processes including a photo-etching process drastically contributes to (i) improvement in productivity of a liquid crystal display device and (ii) a reduction in cost.
In general, it is necessary to carry put the photo-etching process five times in producing the active matrix substrate 71 as described above. With regard to this, Patent Literature 2 discloses a production method which enables a further reduction in manufacturing cost. The following describes a four-mask process disclosed in Patent Literature 1. The four-mask processing achieves rationalization or a reduction in processes by carrying out (i) an islanding process of a semiconductor layer having a channel and (ii) a source and drain wiring process with the use of a single photomask, by a halftone exposure technique.
FIGS. 16 and 17 are plane views each of which illustrates a unit pixel of an active matrix substrate being prepared by the four-mask process. FIGS. 18 and 19 are cross-sectional views which (i) correspond to manufacturing processes shown in FIGS. 16 and 17 and (ii) are taken along lines corresponding to the line A-A′ (insulated gate transistor area), the line B-B′ (electrode terminal area of scanning signal line), and the line C-C′ (electrode terminal area of data signal line) in (b) of FIG. 17. Specifically, (a) of FIG. 16 through (c) of FIG. 16 correspond to the respective cross-sectional views of (a) of FIG. 18 through (c) of FIG. 18, and (a) of FIG. 17 and (b) of FIG. 17 correspond to the respective cross-sectional views of (a) of FIG. 19 and (b) of FIG. 19. Conventionally, two types of insulated gate transistors, i.e., an etch-stop insulated gate transistor and a channel-etch insulated gate transistor are mostly used. The following discusses a case where a channel-etch insulated gate transistor is used as an example.
First, a first metal layer (metal layer for scanning signal line) having a thickness of approximately 0.1 μm to 0.3 μm is deposited on a main surface of a glass substrate 2 (e.g., product name: 1737 manufactured by Corning Incorporated) with the use of a vacuum film-depositing device such as an SPT (sputtering device) (see (a) of FIG. 16 and (a) of FIG. 18). Note that the glass substrate 2 is an insulating substrate having high heat resistance, high chemical resistance, and high transparency, and has a thickness of approximately 0.5 mm to 1.1 mm. Then, a scanning signal line 11, which serves also as a gate electrode 11A, and a storage capacitor line 16 are selectively deposited by a microfabrication technique. The scanning signal line is made up of a material which is selected by comprehensively considering heat resistance, chemical resistance, hydrofluoric acid resistance, and electric conductivity. In general, the scanning signal line is made up of (i) a metal thin film layer made of a material such as Cr or Ta or (ii) an alloy thin film layer made of a material such as MoW, because such thin film layers have high heat resistance.
It is rational to use Al (aluminum) as a material for a scanning signal line in order to reduce resistance of the scanning signal line, in order to deal with an increase in screen size and an increase in definition of a liquid crystal panel. However, Al itself has low heat resistance. In general, therefore, Cr, Ta, Mo, or a silicide of these, which is the above described heat-resistant metal, is stacked on Al nowadays. That is, the scanning signal line 11 is generally made up of one or more metal layers.
Subsequently, three types of thin film layers are sequentially stacked all over the glass substrate 2 with the use of a PCVD (plasma chemical vacuum deposition) device. The three types of thin film layers encompass (i) a first silicon nitride (SiNx) layer 30 having a thickness of, for example, 0.3 μm, (ii) a first amorphous silicon (a-Si) layer 31 with a thickness of, for example, 0.2 μm, which hardly contains an impurity and serves as a channel of the insulated gate transistor, and (iii) a second amorphous silicon layer (n+a-Si) 33 with a thickness of, for example, 0.05 μm, which contains phosphorus as an impurity and serves as a source and a drain of the insulated gate transistor. Then, a source and drain wiring material is formed by sequentially depositing, for example, a Ti thin film layer 34, an Al thin film layer 35, and a Ti thin film layer 36 with the use of a vacuum film-depositing device such as an SPT. Note that the Ti thin film layer 34 is a heat-resistant metal layer having a thickness of approximately 0.1 μm, the Al thin film layer 35 is a low-resistance metal layer having a thickness of approximately 0.3 μm, and the Ti thin film layer 36 is a buffer metal layer having a thickness of approximately 0.1 μm.
Then, (i) a data signal line 12, which serves also as a source electrode of the insulated gate transistor, and (ii) a drain electrode 21 of the insulated gate transistor are selectively formed by a microfabrication technique. Note that the data signal line 12 is configured by stacking a heat-resistant metal layer 34A, a low-resistance metal layer 35A, and a buffer metal layer 36A so that these layers and the gate electrode 11A partially overlap each other. The drain electrode 21 is configured by stacking a heat-resistant metal layer 34B, a low-resistance metal layer 35B, and a buffer metal layer 36B so that these layers and the gate electrode 11A partially overlap each other. According to this selective pattern formation, photosensitive resin patterns 80A and 80B are formed so that a channel formation area 80B (shaded area in (b) of FIG. 16) between the source and the drain has a thickness of, for example, 1.5 μm and a source wiring formation area 80A (12) and a drain wiring formation area 80A (21) have a thickness of 3 μm, with the use of a halftone exposure technique (see (b) of FIG. 16 and (b) of FIG. 18). This is an important characteristic of the rationalized four-mask process.
In general, a positive photosensitive resin is used in producing an active matrix substrate 71. Accordingly, the photosensitive resin patterns 80A and 80B can be formed with the use of a photomask which has a black area, a gray (halftone) area, and a white area. The black area corresponds to the source and drain wiring formation areas 80A in which a Cr thin film is provided. The gray area corresponds to the channel formation area 80B in which a Cr pattern of lines and spaces, which Cr pattern has a width of, for example, approximately 0.5 μm to 1.5 μm, is provided so as to reduce transmitting light through the photomask. The white area corresponds to the other area of the photomask in which the Cr thin film is eliminated. In the gray area, resolving power of an exposure device is deteriorated, and therefore the pattern of lines and spaces is not resolved. This allows light, which is emitted from a lamp light source toward the photomask, to half transmit. This makes it possible to form the photosensitive resin patterns 80A and 80B which have a concave cross section (see (b) of FIG. 18) formed in accordance with a residual film property of the positive photosensitive resin. Note that, instead of providing the slits, it is possible to configure the gray area with the use of a metal layer, e.g., a thin film of MoSi2, which has a thickness and a transmittance different from those of the Cr thin film.
While causing the photosensitive resin patterns 80A and 80B to serve as a mask, the gate insulating layer 30 is exposed by sequentially etching the Ti thin film layer 36, the Al thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 (see (b) of FIG. 16 and (b) of FIG. 18). After that, the thicknesses of the photosensitive resin patterns 80A and 80B are reduced by 1.5 μm or more with the use of an ashing means such as oxygen plasma. This causes the photosensitive resin pattern 80B to be eliminated and accordingly the Ti thin film layer 36 is exposed (not illustrated) in the channel formation area. In this manner, a photosensitive resin patterns 80C (12) and 80C (21), which have reduced thicknesses, are left only in the source and drain wiring formation areas (see (c) of FIG. 16 and (c) of FIG. 18).
While causing the photosensitive resin patterns 80C (12) and 80C (21) to serve as a mask, the Ti thin film layer 36 between the source and the drain lines (i.e., Ti thin film layer in the channel formation area), the Al thin film layer 35, the Ti thin film layer 34, the second amorphous silicon layer 33, and the first amorphous silicon layer 31 are sequentially etched again so that a first amorphous silicon layer (channel section) 31A having a thickness of approximately 0.05 μm to 0.1 μm is left. At this point, a source 33S and a drain 33D, which are made up of the second amorphous silicon layer, are separated from each other. The source line 12 and the drain line 21 are provided by (i) etching the metal layer and (ii) further etching the first amorphous silicon layer 31A so as to be left with a thickness of approximately 0.05 μm to 0.1 μm. Therefore, an insulated gate transistor produced by such a method is called a “channel-etch” insulated gate transistor.
Note that, in the oxygen plasma process, the photosensitive resin pattern 80A is converted into the photosensitive resin pattern 80C having the reduced thickness. It is therefore preferable to improve anisotropy in order to suppress a change in size of the pattern. Specifically, it is preferable to employ an oxygen plasma process such as of an RIE (Reactive Ion Etching), more preferably, an ICP (Inductive Coupled Plasma) or a TCP (Transfer Coupled Plasma) using a source of plasma with higher density.
Moreover, after the photosensitive resin patterns 80C (12) and 80C (21) are eliminated, a passivation insulating layer 37 as a transparent insulating layer is formed by depositing a second SiNx layer, which has a thickness of approximately 0.3 μm, all over the glass substrate 2. Then, an opening 62 is formed above the drain electrode 21, an opening 63 is provided above an area in which an electrode terminal of the scanning signal line 11 is to be provided, and an opening 64 is provided above an area in which an electrode terminal of the data signal line 12 is to be provided (see (a) of FIG. 17 and (a) of FIG. 19). Note that the areas, above which the openings 63 and 64 are provided, and an image display section do not overlap each other. Further, (i) the passivation insulating layer 37 and the gate insulating layer 30 are eliminated from the opening 63 so that a part 5 of the scanning signal line is exposed in the opening 63, (ii) the passivation insulating layer 37 is eliminated from the opening 62 so that a part of the drain electrode 21 is exposed, and (iii) the passivation insulating layer 37 is eliminated from the opening 64 so that a part 6 of the data signal line is exposed. Similarly, an opening 65 is formed above the storage capacitor line 16 so that the storage capacitor line 16 is partially exposed.
Lastly, for example, an ITO (Indium-Tin-Oxide) or IZO (Indium-Zinc-Oxide) or a mixed crystal of them is deposited as a transparent conductive layer having a thickness of approximately 0.1 μm to 0.2 μm, with the use of a vacuum film-depositing device such as an SPT. Then, a transparent conductive pixel electrode 22 is selectively provided so as to cover the passivation insulating layer 37 and the opening 62, with the use of a microfabrication technique (see (b) of FIG. 17 and (b) of FIG. 19). This is how the active matrix substrate 71 is produced. The storage capacitor 15 (see FIG. 14) is defined by the drain electrode 21 and the storage capacitor line 16 which two-dimensionally overlap each other via the gate insulating layer 30, the first amorphous silicon layer 31A, and the second amorphous silicon layer 33D (see (b) of FIG. 17 and (b) of FIG. 19). The storage capacitor 15 is also indicated by an area 50, which is shaded with diagonal lines, in (a) of FIG. 18. Moreover, an electrode terminal 5A is selectively formed above the passivation insulating layer 37 and the opening 63, and an electrode terminal 6A is selectively formed above the passivation insulating layer 37 and the opening 64.
In a case where the source line 12 and the drain line 21 are made of an Al material as described above, it is necessary to provided the heat-resistant metal layer 34 in order to secure an electrical connection between (i) the second amorphous silicon 33 and (ii) the source line 12 and the drain line 21. Moreover, it is necessary to provided the buffer metal layer 36 between (i) the transparent conductive layer and the (ii) the source line 12 and the drain line 21 in order to prevent a battery effect in an alkaline solution. Consequently, the source and drain lines are to be configured by a three-layered structure. Nevertheless, it is difficult to avoid using the low-resistance metal layer (Al thin film layer), in order address a severe restriction in terms of the resistance of the source and drain lines in a liquid crystal panel with a large screen and high definition.
Conventionally, in a case where the heat-resistant metal layer 34 and the buffer metal layer 36 are made of Ti, it is necessary to carry out a dry etching process with the use of chlorine gas. Accordingly, the Al is subjected to the dry etching process with the chlorine gas. This causes a burden in terms of material and production equipment. However, in these days, new chemicals for etching Ti have been provided by Mitsubishi Chemical Corporation. This has improved a possibility to reduce burden of investment in the production equipment. In a case where the heat-resistant metal layer 34 and the buffer metal layer 36 are made of Mo instead of Ti, a three-layered configuration of Mo/Al/Mo is usually subjected to a chemical treatment once with the use of a phosphate solution to which an appropriate amount of nitric acid is added. It is therefore easily understandable that cost of investment in the production equipment can be suppressed. Moreover, it is self-explanatory that various efforts have been made in order to reduce production cost by simplifying the source and drain lines as much as possible.